This invention relates to semiconductor memory devices, and more particularly to improved dummy cell circuitry in dynamic memory devices.
Dynamic MOS read/write memory devices have been constructed generally as shown in U.S. Pat. No. 3,940,747 (a 4K dynamic RAM) issued to Kuo, U.S. Pat. No. 4,081,701 (a 16K dynamic RAM) issued to White, McAdams and Redwine, or U.S. Pat. No. 4,239,993 (a 64K dynamic RAM) issued to McAlexander, White and Rao, all assigned to Texas Instruments.
In these and other prior devices a row of dummy cells on each side of each differential sense amplifier was used as a reference input. The capacitors in the dummy cells were about one-half the size of the storage capacitors, and typically the dummy capacitors were predischarged to ground. So, the signal produced in the bit lines by the dummy cells was about half way between that produced by a one and that produced by a zero in the storage cell.
When the cell size is reduced to the level needed to manufacture high density memory devices of 256K-bit or 1-Megabit and beyond, the problem of forming the dummy capacitors at the proper ratio to the storage capacitors becomes formidable, from a process standpoint. A slight variation in the process conditions results in a much greater change in value of the smaller capacitor than the larger.
It is the principal object of this invention to provide improved circuitry for high density dynamic RAM devices, particularly dummy cell circuitry. Another object is to provide dummy cell circuitry for a dynamic RAM in which the dummy cell capacitors are the same size as the storage capacitors. A further object is to provide dummy cell circuitry which can be manufactured without adverse effects of process variations upon the dummy cell size.